1

An Expurgated Union Bound for Space-Time Code Systems

First Author

LNCS (Springer-Verlag), Vol. 3124

2004

2

Analyzing the Performance of Mesh and Fat-Tree topologies for Network on Chip design

First Author

LNCS (Springer-Verlag),Vol. 3824

2005

3

Designing On-Chip Network based on optimal latency criteria

First Author

 LNCS (Springer-Verlag) Vol. 3820 

2005

4

The Optimum Network on Chip Architectures for Video Object Plane Decoder Desig

First Author

LNCS (Springer-Verlag), Vol. 4330

2006

5

Throughput aware mapping for Network on Chip Design of H.264 Decoder

First Author

 LNCS (Springer-Verlag), Vol. 4331

2006

6

Realization of Video Object Plane Decoder on On-Chip-Network Architecture

Co-Author

 LNCS (Springer-Verlag), Vol.  3820

2005

7

Latency Optimization for NoC Design of H.264 Decoder Based on Self-similar Traffic Modeling

First Author

 LNCS (Springer-Verlag), Vol. 4742

2007

8

An QoS Aware Mapping of Cores Onto NoC Architectures

Co-Author

LNCS (Springer-Verlag), Vol. 4742

2007

9

Performance and Complexity Analysis of Credit-Based End-to-End Flow Control in Network-on-Chip

Co-Author

LNCS (Springer-Verlag), Vol. 4742

2007

10

Tightening union bound by applying Verdu theorem for LDPC

First Author

IEEE PIMRC2003

2003

11

Expurgated Tangential Bound of Low Density Parity Check

First Author

 IEEE CSNDSP2004

2004

12

Expurgated Sphere Bound of LDPC

First Author

IEEE PIMRC2004

2004

13

On Chip Network: Topology design and evaluation using NS2

First Author

 IEEE ICACT2005

2005

14

Designing Network on Chip based on Fat-Tree topology

First Author

IEEE ICT2005

2005

15

On-Chip Network latency analysis and optimization using Branch and Bound algorithm

First Author

ITC-CSCC2005

2005

16

Realization of Video Object Plane decoder on Mesh On Chip Network Architecture

Co-Author

IASTED CSS2005

2005

17

Implementation of H.264 Decoder on On-Chip-Network Architecture

Co-Author

 ISOCC2005

2005

18

An optimum mapping of IPs for On-Chip Network design based on the minimum latency constraint

First Author

 IEEE Tencon2005

2005

19

The Optimized Tree-based Network on Chip Topologies for H.264 Decoder Design

First Author

 IEEE ICCES’06

2006

20

Multiplane Virtual Channel Router for Network-on-Chip Design

Co-Author

 IEEE HUT-ICCE’06

2006

21

A Virtual Channel Router with Wavefront Allocation Scheme for On-Chip Network

Co-Author

 IEEE HUT-ICCE’06

2006

22

Realizing Network on Chip Design of H.264 Decoder Based on Throughput Aware Mapping

First Author

 IEEE HUT-ICCE’06

2006

23

Assessing Routing Behavior on On-Chip-Network

Co-Author

IEEE ICCSC’06

2006

24

High-rate Space-Time Block Coded Spatial Modulation

Co-Author

IEEE ATC’12

2012

25

A Novel Spatially-Modulated orthogonal Space-Time Block Code For 4 Transmit Antennas

Co-Author

IEEE ISSPIT’ 12